July and August 2026
Llama 3.1 8B on AWS Trainium and Inferentia
A LoRA fine-tune on one Trainium1 and one Trainium2, served by vLLM on one Inferentia2, measured beside one MI300X and one H200 with the same request shape.
Google TPU, AWS Trainium and Inferentia, Intel Gaudi: what runs on them, what a token costs against a GPU, and where the compiler stops you. One study measured on the chips, and the tools and talks around it.
July and August 2026
A LoRA fine-tune on one Trainium1 and one Trainium2, served by vLLM on one Inferentia2, measured beside one MI300X and one H200 with the same request shape.
Calculator
Can that model run on that ASIC? Memory math and compiler support for Google TPU, AWS Trainium and Inferentia and Intel Gaudi against NVIDIA GPUs, every spec cited.
Agent skills
Claude Code and Codex skills for Google TPUs: Pallas kernels, XProf profiling, XLA compiler artifacts and PyTorch/XLA lowering problems.
PyTorch Europe conference talk
De-mystifying PyTorch for ASICs
The talk's code and assets. Its companion repository fine-tunes three models, SFT then DPO with LoRA, on both GPU and TPU.
Talk code, DevFest 2025
Google TPU code for our talks: PyTorch/XLA basics, MNIST, and inner and outer products the way a systolic array computes them.
Code
Deep-learning projects on Trainium1 instances, starting with MNIST, and a write-up of why it first trained on the CPU instead.